I. Technical Field
The present invention relates generally to techniques for protecting integrated circuit intellectual property from unauthorized use. More particularly, the present invention relates to creating content-encrypted silicon IP layout database.
II. Background
Electronic systems are built in large part using standalone, individually packaged chips, which are assembled on printed circuit boards (PCBs) and connected together to obtain the desired functionality. The electronic industry is currently shifting towards a new design paradigm called as SOC, (an acronym for “System on a chip”). Under this paradigm, all the necessary electronic circuit blocks are integrated onto a single chip to come up with a complete electronic system that performs more complex and more useful functions. Compared with the PCB multi-chip systems, the SOC systems usually consume less power, occupy less space and have a lower cost and higher reliability.
Meanwhile, the continuously increasing number of electronic circuit blocks that electronic companies are fitting onto a single chip has been driving the need for a correlating increase in developer productivity. Circuit developers are increasingly acquiring electronic circuit blocks from other sources and incorporating them into their designs as a strategy to enable them to more quickly complete designs and focus their engineering resources on their core competencies. The acquired electronic circuit blocks are alternatively referred to as IPs, (an acronym for “Intellectual Properties”). IP usually by nature has been pre-tested and pre-verified and is reusable, for example, a micro-controller IP in a cellular phone system could be reused in a digital TV set-top box or in an automotive application.
There are mainly two types of IPs. One type is software IP. Software IP, which is commonly presented in the form of a HDL (hardware description language) file, provides functional description of a circuit design. Another type of IP is silicon IP. Silicon IP, which is presented in the form of a layout database, such as GDSII file or OASIS file, is specific in a certain foundry technology and provides layout mask level description of a circuit design. Silicon IP is always silicon-proven, which means, it already has a successful wafer fabrication and has a satisfied yield rate of production. For the same functionality circuit design, compared with software IP, silicon IP requires electronic companies to put much more time and much more financial and engineering resources to achieve.
Since silicon IP is presented in GDSII (Graphic Data System II), OASIS (Open Artwork Systems Interchange Standard), or other format layout database electronic files and physically exist on magnetic storage devices, the silicon IP is relatively easy to copy, forge and re-design. Moreover, the increased efficiency brought about by the existence of silicon IPs also provides an incentive for unauthorized use, re-use transfer or sale of these items. Silicon IP providers, are therefore in need of an effective method of protecting their designs, so that they are not deprived of the benefits of the resources spent in silicon IP design development. Additionally, silicon IP is foundry technology specific, which may expose confidential technology information of the foundry. Silicon IP providers also receive essential requests from the foundry to find an effective method to hide the confidential foundry information in their silicon IPs.
Traditionally, silicon IP protection has largely been through legal means such as non-disclosure agreements, patents or copyrights. By themselves, however, such legal means are of limited use, because detection of illegal copying, forging, transfer or re-use of proprietary silicon IPs is difficult. It can be challenging to determine whether a silicon IP was illegally acquired by a particular user. The user, for example, may make superficial changes to the silicon IP to disguise its illicit source. Furthermore, the costs involved in preventing unauthorized copying, re-use or transfer of silicon IPs, and in discovering whether particular silicon IPs have been illegally acquired, can be excessive.
One conventional method, which has been used in an attempt to protect silicon IP, is a technique known as “tagging.” Tagging involves the creation of an electronic document containing information about the ownership of the silicon IP. The electronic document, in text form, is typically embedded into the silicon IP at the layout mask level. However, because text at the mask level may be easily removed, tagging is not especially effective.
Another method used to protect silicon IP is a “watermarking” technique. Watermarking embeds a hidden, recognizable input/output signature into the circuit design. That is, it uses an internal sequential function, such as a finite state machine, to generate a predictable output sequence when a known input sequence is applied. Thus, the input/output signature can be used to identify the silicon IP's ownership. However, a shortcoming of this watermarking technique is that unauthorized deletion of the watermark is still possible. However, when the silicon IP is integrated into an electronic system design, at the layout mask level, its input/output pins may become internal connection paths and be covered by other mask layers. Hence, it is hard to access the input/output pins and validate the silicon IP's input/output signature.
Furthermore, both “tagging” and “watermarking” techniques are passive methods to protect the silicon IPs' ownership. The “tagging” and “watermarking” techniques can be used to detect or collect evidence on any illegal use of a silicon IP in litigation, but they can not be used to hide the actual intellectual property (IP). The confidential foundry information, the key technology and essential design ideas of the silicon IP can still be easily lost through any illegal studying and analyzing of the silicon IP's layout database.
The cryptography based IP protection method introduced in “Methodology for protection and licensing of HDL IP” appearing in D&R industry articles (March 2006), can effectively use public encryption algorithm to protect software IPs. But it is not capable of operating on the layout database, so it can not be adopted as a valid method to protect silicon IPs. Another encryption related method uses an encrypting program to encrypt the whole silicon IP layout database. But after encryption, the output file is no longer in the original layout database format, and can not be commonly accepted by the electronic design automation (EDA) software tools and utilized as a circuit design block in a SOC design. Thus, such an encryption method is not an applicable solution.
There is a need for a more effective technique for protecting the silicon IP from unauthorized copying, re-use, transfer or sale. There is further a need for such a silicon IP protection technique that is cost-effective yet relatively simple to implement, and resistant to tampering by the user.
Given the anticipated growth in commerce related to silicon IP, the electronic circuit design industry is in dire need of a method of protecting their silicon IP that is more effective and affordable than existing schemes.